CS 252
Graduate Computer Architecture
Fall 1996 Semester Project:
IDEA as a Benchmark for Reconfigurable Computing
PEOPLE
ABSTRACT
There is an increasing interest in using reconfigurable hardware for
performing computational tasks. Yet despite this interest, there are
no suitable metrics for comparing the performance of reconfigurable
systems. We propose that the core encryption of the International
Data Encryption Algorithm (IDEA), a popular 128-bit block cipher, be
used for this purpose. We implemented the IDEA algorithm on two
classes of reconfigurable devices, the
Xilinx 4000 series
of field programmable gate arrays and the proposed
Garp
(Gate Array Risc Processor, part of the UC Berkeley
BRASS
project) reconfigurable array. The performance on these two devices was
characterized and compared with other implementations.
THE PAPER
LINKS
- CS 252
Fall 1996 course home page
- Reconfigurable architectures:
- BRASS
- Berkeley Reconfigurable Architecture, Systems, & Software
-
Garp - Gate Array RISC Processor
- Xilinx - makers of commercial
FPGAs
-
DPGAs - Dynamically Programmable Gate Arrays,
Andre DeHon
- Non-reconfigurable architectures:
Last Updated: 8/30/97
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