Scheduling for Virtualized FPGA Hardware
Abstract
Reconfigurable computing devices offer substantial improvements in
functional density and yield versus traditional microprocessors, yet they
remain out of general-purpose use due in part to their difficulty of
programming and lack of cross-device compatibility. This project
presents a reconfigurable architecture which supports automated
compilation and cross-device compatibility by virtualizing hardware
resources and automating management thereof in operating system
services. A study of architectural parameters indicates that this
architecture would benefit from small time slices on the order of a
millisecond, and from a high availability of configurable memory
resources. A dynamic scheduling algorithm is presented whose
effectiveness is found to depend heavily on clustering and
co-scheduling of virtual compute operators.
Last updated: 12/15/98
Comments to:
eylon@cs.berkeley.edu